Chemical mechanical planarization (CMP) is a popular method of planarizing the surface of a semiconductor substrate. CMP combines chemical etching and mechanical polishing to remove raised features on the surface of the semiconductor substrate. Planarity of the surface is a critical dimension for integrated circuit fabrication.
Standard practice is the use of a polishing pad mounted on a flat rotating platen, or turntable. The substrate is held in a carrier facing down and in contact with the polishing pad on the platen. The WIW (with-in-substrate) and WID (with-in-die) non-infirmities on the substrate surface are addressed by adjusting the back-pressure on the substrate, which in turn, alters the substrate's local shape with respect to the polishing pad. Platen to carrier rotational speed and carrier oscillation are also utilized to address these issues. Both approaches have their limitations due to the limited number of process parameters that can be controlled.
In an effort to increase production efficiencies, larger substrate sizes are becoming available. The current method for CMP is not adequate for these larger sizes. The polish non-uniformities are amplified with the increase in substrate diameter, which can contribute greatly to the WIW (with-in-substrate) and WID (with-in-die) non-uniformities.
The move of the industry toward using low and ultra low-K materials is also challenging current CMP processes. Metal delamination during the planarization process is caused by the weak adhesion between the low-K dielectric and the metal layer. CMP of low-K and ultra low-K substrate requires a process that provides low applied pressure and high velocity that is not easily obtainable with the current methods due to the limited number of process parameters that can be controlled.
Suitable apparatus and methods are needed for planarizing larger substrate, as well as improving the planarization of all substrate sizes, that are more reliable, consistent, and uniform.